Multithreaded Architectures
- Hardware-support for many fine-grained processes (threads).
- Multiple program counters.
- Multiple register files.
- Very efficient context switch.
- Possibly after each instruction.
- Memory latency can be hidden.
- Thread blocked on read of remote memory cell.
- Other threads executed in the meantime.
- Sufficient parallelism required:
- Instruction-level parallelism.
- Application-level parallelism.
- Example: Tera MTA (Multi-Threaded Architecture)
Future of processor architectures.
Author: Wolfgang Schreiner
Last Modification: December 23, 1997