Go backward to Design Goals Go up to Top Go forward to Mapping Strategies

Loop Interchange

• Parallelization of outer loop.
• Row-major layout of matrices (C).
• Outer loop $i$
  • Rows of $A,C$ distributed among processors.
  • $B$ accessed colum-wise by every processor.

  

• Outer loop $j$
  • Columns of $A,C$ distributed among processors.
  • $B$ accessed row-wise by every processor.