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All distributed memories are transformed into caches.
No memory hierarchy at processor node.
All caches form a global address space.
Example: KSR-1 computer with ALLCACHE memory.
Each address becomes a
without direct physical relevance.
Processors form a two-level ring structure; a directory scheme associates names to processors.
A search engine transfers memory cells to processors as needed.
Prefetch mechanisms are supported to get required data ahead of time.
Problem: Processor are blocked during wait for memory cell.
Last modification: November 15, 1996